As Si interposer and 3D stacked memory devices enter into production, albeit in low volumes, semiconductor manufacturers are lining up their ducks to be ready for high volume manufacturing (HVM) when it happens. As a result, some suppliers of high volume manufacturing equipment who have been rather quiet through the development phase are now showing their cards. For example, KLA-Tencor recently introduced its line of advanced wafer level packaging (AWLP) inspection and metrology tools to the market, targeting both 3D IC and fan-out wafer level packaging (FOWLP). CIRCL-AP is a fully automated platform that integrates wafer front-side and edge inspection and review. The ICOS T830 component inspection system completes the wafer-to-package process control offering. I recently sat down with Lena Nicolaides, VP and General Manager, SWIFT Division, KLA-Tencor, to get her take on the FOWLP and 3D IC markets, and also learn more about KLA-Tencor’s activities in this space.

The Back Story
When asked to define KLA-Tencor, Nicolaides doesn’t use the term “equipment manufacturer,” rather, she says: “We are a process control company that provides inspection and metrology solutions to our customers. We help customers improve yield, which helps control cost.” The company, which was formed in April 1997 through the merger of KLA Instruments, an inspection company, and Tencor Instruments, a metrology company, is well known for its expertise in front-end process control. Combining inspection with measurement provides an overall loop for improved process control, explained Nicolaides.

In 2008, KLA-Tencor acquired ICOS. The recent introduction of the CIRCL-AP and ICOS T830 completes the evolution to offer wafer and component inspection in the back end.

Although it may appear that KLA-Tencor is new to AWLP, that isn’t the case. The company actually began engagements four years ago with a memory customer who saw solutions in the company’s CIRCL (which stands for concurrent inspection and review cluster) wafer inspection platform for 3D IC processes. “They asked us, ‘can you modify the CIRCL system to provide inspection at certain process steps for 3D IC?’” recalled Nicolaides. It turned out that because the middle-end-of-line (MEOL) processes specific to 3D ICs aren’t typical back-end processes, their front-end tool could measure critical steps that other systems were blind to. The company placed 3 systems customized for 3D IC with the customer, and has also since engaged with various consortiums including imec and IME, all geared towards TSVs and higher end applications.

Ironically, although FOWLP is taking off faster than 3D IC in manufacturing, KLA-Tencor’s platform was first developed for 3D IC processes, noted Nicolaides. Then as FOWLP ramped to production and manufacturers were looking for ways to lower cost and improve yields, they realized that technologies developed for 3D IC could be implemented for FOWLP. “We found ourselves able to provide solutions to the OSATs,” noted Nicolaides.

The IoT Impact
“We are benefiting from the Internet of Things (IoT)” said Nicolaides. Initially, she sees demand for FOWLP growing on the consumer product side, but as device functionality becomes more complicated, 3D will be required. For example, the automotive market is a huge growth area for semiconductors overall. According to IC Insights, there is already $425 worth of chip content per car, and this number is expected to double over the next 5 years. Moreover, car manufacturers are already looking at 3D. At ISS Europe in February, a representative of Audi announced that TSVs will be in automotive electronics “very shortly.”

Of the six major end-use applications for ICs, the automotive IC market is forecast to experience the strongest average annual revenue growth rate through 2018. (source: IC Insights)

“The automotive industry is all about zero defects,” explained Nicolaides. “We have to inspect every die and every wafer.” As such, automotive manufacturers are willing to pay more.

How Do We Lower Cost?
In the OSATs world cost is king. Improving yield and automating inspection processes are two ways to lower manufacturing cost, regardless of the device being built. Historically, inspection requires operator review of many images to find defects. Nicolaides explained that what the OSATs are looking for is a way to improve yield at a reduced cost by reducing the number of images needed, as well as the number of people required to review them.

“You can’t improve yields if the systems you’re using are blind to killer defects,” said Nicolaides. “Customers are coming to us saying they need better sensitivity and better capture rate. This is music to our ears because we already have solutions to enable the industry, even for 3D IC, to make it cost effective.”

Nicolaides further explained the advantages of automated defect inspection and binning that are the hallmarks of the CIRCL-AP and ICOS T830 systems. Sensitivity and capture rates help with yield overall, and when it’s automated, the results are more consistent and require fewer operators to perform the inspection. “Customers looking for automated tools are an indication that we’re headed to volume production,”

A comparison study between manual inspection and automated inspection proved that the automated tool not only found more defects of interest (DOI) than manual operators, it could also classify and bin them by defect type. In the study, one operator found 10 defects. A second operator found 30. The tool found 50. Additionally, there were few common defects between the two operators, but the tool found them all.

Not all are killer defects, said Nicolaides, some just require improved processes to eliminate them. Systems without a good capture rate can generate a lot of “noise;” capturing something that’s not real. 50% of these are not real, and require many operators to review them and decide which are real. Nicolaides explained that with the CIRCL-AP, the capture rate is high, eliminating the need for manual review. High throughput means fewer tools. All this translates to lower operating expenses.

“When we were entering the market, many players didn’t realize the differentiation between the defects,” noted Nicolaides. “The timing for us is phenomenal. We’re coming in at a time where the industry is looking to reduce cost, while additionally looking to next-generation requirements.”

Defining Volume Production for 3D IC
“Customers looking for automated tools are an indication that we’re headed to volume production,” noted Nicolaides. A memory company is setting up a pilot line for memory stacking. It may be small volumes, but it’s still HVM for them. “It’s enough to consider it HVM,” commented Nicolaides. “And it’s more than people would have expected. 3D is transitioning and we fully believe in the next few years we’ll see more because the functionality and performance that comes from 3D IC is incomparable.”

Nicolaides predicts that four years from now, we’ll see 3D ICs in more devices as costs continue to be improved. “The inflection point that’s happening today involves improving overall cost and yield in the backend,” noted Nicolaides. “KLA-Tencor can play a role in that—that’s what excites me.”

Even if it would be relegated to high performance computing and memory, the growth of 3D IC in these two areas of the industry is sufficient to make it worth the investment. ~ F.v.T.

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The Xilinx Ultrascale VU440 3D FPGA is constructed using “Xinterposer” 3D IC technology jointly developed by Xilinx and TSMC. It uses a low-k dielectric chip fabricated on 20nm silicon node with a total of 375,000 micron bumps stacked on 25mm x 45mm silicon interposer and assembled with CoWoS. The composite 3D FPGA consists of approximately 19 billion transistors.

Testimonial:
The Ultrascale VU440 represents a silicon interposer product on the largest interposer fabricated with a size exceeding the reticle. Field stitching is used for the lithography as it surpasses the size of the reticle. The Interposer is mounted with C4 bumps on a 55mm x 55mm organic substrate. The silicon interposer has acceptable warpage/coplanarity and passed 1,000 TCB and 1,000 hours HTS without any failure or voiding in the low-k, micro bumps or C4 bumps.

Xilinx Website
Date this Product was Introduced to the market: May 2015
Category Product is Being Nominated for: Devices (including interposer, 3D IC, 3D Memory, Heterogeneous Integration)
Technical Documentation for the Ultrascale VU440

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I was invited to attend Amkor’s bi-annual customer symposium, which was held in Santa Clara two weeks ago. It was a grand event, complete with rock music intros narrated by a disembodied Voice of Authority for the execs (wait, was that AC/DC’s Back in Black I heard as CEO Steve Kelley took the stage?), inspirational TED-talk like presentations, and a motivational keynote about (you guessed it!) the Internet of Things by Chad Jones, CTO of Deep Information Systems. There were some nifty door prizes (I came THIS close to winning an iPad mini and a $200 gift card to Best Buy – which would have gone toward a new Smart TV, I guarantee it), and useful swag (my new earbuds have already been broken in). But mostly, it was a day chock full of enthusiasm for the future of advanced packaging, and lots of great information on Amkor’s offerings for each segment of the market.

John Stone, EVP, worldwide sales and marketing, set the tone for the day, with the phrases, “if you can imagine it, you can connect it” and a promise that “If you can envision it, we can enable it.” It’s clear that the predictions we made at Solid State Technology (then Advanced Packaging) back in 2007 are finally coming true: Packaging Saves the World. 

“Power management, content delivery, sensors, and smaller/thinner devices is what is driving new designs,” says Stone. As such, the industry is in the midst of a paradigm shift with new enabling packaging at its center.

What’s the next game changer? According to Stone, the mobile market has slowed, but the automotive market has embraced the IoT, with $520 worth of packaged content throughout each car including the chasis, power train, security, safety, comfort, control, infotainment, etc. Home automation, the smart grid, and medical are other areas of growth. “We’re just at the beginning of this, and it’s enabled by new devices.”

Stone talked about China: “It’s not about competing WITH China, it’s about competing IN China… and Amkor is one of the only companies that has the ability to do this.” He also talked about Amkor’s new leadership team, headed by CEO Steve Kelley, and the company’s “culture of YES” with the focus on solutions not problems.

Kelley laid out Amkor’s investment strategy for the future. The company was a pioneer of the OSAT concept, he said, and at over $3B in sales is now the world’s second largest OSAT. The goal is to reach over $5B in sales over the next 3-5 years by focusing on the basics of quality and execution. He broke down the company’s revenue by market:
• 56% communications
• 13% consumer products (TV set top boxes, gaming)
• 11% networking
• 11% automotive infotainment, safety and performance
• 9% computing (hard disk drives)

“Our strategy is about 2 things; meeting customer needs and filling our factories,” said Kelley. “We lead with advanced technologies, and drive sales through execution, quality, and ease of doing business.” He added that as a high fixed cost company, success is determined by filling capacity, which they do through acquisitions and strategic investments. One of those strategic partnerships is with J-Devices, a Japanese OSAT with deep connections in the Japanese automotive market, of which Amkor owns 66%.

While communications is currently the biggest market segment for Amkor, automotive is the fastest growing, and with the Japanese market showing the highest percentage of IC content per car at $950/vehicle, due to safety and environmental requirements, a partnership with J-Devices is very advantageous. “Suppliers have challenges in the Japanese automotive market,” explained Yoshio Yoshimura, Sr. Director, ATJ Sales. “Japan has the highest hurdles for product qualification, uncompromising demand for zero defect, and requires relationships and local support in Japan. We can get you connected in Japan.”

Kelley also stressed the company’s 15-year investment developing system in package (SiP), which is increasing further still, driven by smartphones and tablets, and now automotive and the IoT. Lastly, he announced the opening of th K5 factory and R&D facility near Incheon Airport, in South Korea, noting its excellent logistics, as well as advanced packaging and test capabilities.

Ron Huemoeller, Senior VP, technology development and IP, provided the executive perspective for technology development in the connected world, also providing updates on interposer devices with and without through silicon vias (TSVs), and also differentiated between the companies’ wafer level packaging platforms (Figure 1).

Figure 1: Amkor’s Advanced wafer level package options and positioning. (courtesy of Amkor).

To “humanize” how far we’ve come in the tech industry, Huemoeller talked about vacationing in the Maldives, a little island in the middle of the Indian Ocean that took five flights and a boat to reach, but had good cell and Internet service. “Internet access is increasing, and it’s all about data usage,” he said. “We’ve got 90% penetration rate in North America and Europe. 50% in China, and 25% in India. There is still opportunity for growth.” He added that the data rate is expected to double over the next five years. Big Data, driven by video streaming, such as Netflix and Youtube, is driving the infrastructure needs, network and storage. For Amkor, this translates into an increased production of FCBGA, CABGA, SCSP, QFP, QFNs, Cu pillar and…wait for it…die stacking!

He echoed Kelley and Jones’s enthusiasm for growth in the automotive market, as well as the IoT. “The IoT circle of influence is growing, from automotive, to connected homes, connected cities, medical, and the industrial IoT,” noted Huemoeller. System-in-package (SiP) is a big growth sector for this, particularly because it requires a combination of solutions such as RF, sensors, and microcontrollers. 3D WLCSP is a way to integrate more content using multi-die stacking, wafer level processes, and TSVs. “TSV will eventually come into play as we need that connectivity and can no longer be served by wire bond,” he said. “We innovate with cost in mind, not just to push technology forward.”

According to Huemoeller, Amkor has shipped more than 40K 3D assembled units to date. He said the TSV interposer business is moving beyond networking to graphics products. The company has shipped more than 25K assembled units comprising multiple logic and/or memory die on thinned interposer. And there’s more where that came from.

“The line is ready to go,” said Huemoeller, “I don’t think we’re the only ones launching more 2.5D.” The hold up, he said, was lack of a memory standard. “Now that HBM is available, more people will design it in. The bandwidth is so much more than you can get from standard memory,” he said.

Another critical factor to increasing volumes was the availability of HBM from more than one source. The quality of interposers has improved and number of suppliers has increased. Prices are dropping to half of what they were 4-5 years ago, noted Huemoeller, opening doors to new products in the high performance space.

The question is, how do we get these architectures beyond high performance into other applications? The progression goes from the high performance to what Huemoeller calls “the enthusiast market” and then the consumer mobile products.

Amkor’s path there is through its latest product offering, silicon-less integrated module (SLIM), which requires no TSVs, passivation or CMP. Both thinning and etch are simplified. Essentially, it’s a lower cost product that’s no longer tied to the TSV supply chain. Still in development, SLIM is coming in the next 3-4 years.

Huemoeller also talked about silicon wafer integrated fan-out (SWIFT), the company’s most advanced FOWLP for high-level applications. The main difference between traditional FOWLP and SWIFT is that it’s a dies first vs. dies last approach. Die first is subject to yield loss, whereas with die-last, there is less risk to the die because the expensive processes are performed first.

With regard to a technology timeline, Huemoeller said the company is production-ready for TSV, with enough capacity to serve customers. By 2016, they expect to be rolling out TSV interposer products with logic and HBM. SLIM multi-chip modules will also appear in 2016, and TSV logic-on-logic devices will make an appearance in 2017.

I purposely did not write about Chad Jones keynote here, because quite frankly, I’m still digesting his words, and it merits a post all its own. Stay tuned! You’re going to want to read that one too. ~ FvT.

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Amkor’s SLIM (siliconless integrated module) is a dies-last package technology providing the thinnest possible form factor with the highest level of integration by use of back-end-of-line technology combined with assembly-based fan-out architectures.  It has optimal registration, 3D access to top and bottom side of package and the finest line RDL capability found in packaging today!

Testimonial
SLIM is a lower cost, higher bandwidth package technology that improves both 2.5D and fan-out architectures with respect to RDL, profile and yield.  Its the industry’s most advanced packaging technique available today.

Amkor Website
Date this Product was Introduced to the market: November 2014
Category Product is Being Nominated for: Devices (including interposer, 3D IC, 3D Memory, Heterogeneous Integration)
Technical Documentation for SLIM

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By attracting 7011 EDA and IP developers and users, the 52 Design Automation Conference, held in the South Hall of San Francisco’s Moscone Center in the week of June 7, achieved a 14.5% increase in attendees. I was one of them, and started on Sunday evening by listening to Gary Smith’ EDA Forecast presentation. Based on Gary’s and Laurie Blach’s analysis, EDA is likely to grow by 11.2 % annually to reach US $9B by 2019. This prediction includes IP – for which Gary predicted fairly flat revenue of about $3B/year – our industry will grow to $12B.

Gary attributed the flat IP revenues to how difficult it is now to get royalties, and to traditional mega cells being free. However, he is optimistic about the revenue growth of complex platform designs like ARM is offering.

While revenues for PCBs and MEMS are included in his EDA numbers, Gary pointed out that the market for mechanical CAD tools is actually bigger today than for EDA tools and has a very bright future, especially if (when?) both EDA and MCAD developers work together to offer customers a design continuum. Other areas for growth, in Gary’s view, are development tools and IP for ultra-low power applications, optical designs, applications software, and design tools for the fast growing market of electronic devices for the automotive market. Many exhibitors must have come to the same conclusion – or have talked to Gary or Laurie before DAC – because if there was a market-focus at DAC 2015, it was clearly Automotive.

My work on various consulting projects and my 2015 BMW X1 clearly confirm that smart, user-friendly and reliable electronics can add a lot of value to a car, SUV, truck and other vehicles. What I also see is that products for automotive, IoT, even consumers need to address not only multi physics parameters, but also chemical and even biological characteristics.
A perfect example for creating value with a solution that utilizes multiple sciences was Monday’s keynote. Google’s Brian Otis impressed most of us by showing how Google developed a contact lens for diabetics.
Instead of me explaining the deployed mechanical, electrical and biological concepts, I recommend you spend 24 minutes listening to Mentor’s Anne Circle and her introduction of DAC 52. Then enjoy Brian’s 50 minutes presentation about “Google smart lens. IC design and beyond”. You’ll see how much value can be created with inter-disciplinary ideas and development cooperation across multiple sciences.

As I mentioned above, DAC 52 addressed a number of automotive topics, as did Tuesday morning’s keynote.
But before, in the first Tuesday keynote, Intel’s Vivek Singh eloquently addressed: “Moore’s Law at 50: No end in sight” He made very valid points why high-volume applications can and will benefit from 10 and 7 nm technology. Economics will show how high production volume and profit margins need to be, to pay back the development and tooling cost of these advanced technologies.
For the second keynote Jeff Owens, CTO and EVP at Delphi Automotive took the stage and presented: “The design of innovation that drives tomorrow”. Again, follow his presentation at this link, but also allow me to mention a few points I found really educational:

• A premium car today uses 50 computers and 100M lines of code, while an F35 fighter plane “only” needs 24M.
• Delphi employs about 20,000 engineers; 5,000 of them are software engineers
• 100 million cars will be produced worldwide in 2020; 30 million of them in China
• In about 10 years there will be 50% more vehicles on the road worldwide, compared to today
• Currently about 50% of the world population lives in cities; this number will grow to 70% by 2050
• Within the next 10 years China will add 350M urban residents – the current population of the U.S.

These and other technology- and market challenges motivate Delphi Automotive to focus their efforts in three over-arching areas: SAFETY, GREEN and CONNECTIVITY.

• Safety: 90% of accidents happen because of driver error. Technology will help avoiding most of them.
• Green: While 90% of the vehicles in 2040 will rely on combustion engines, their fuel efficiency (~100 miles/g) and emissions reduction measures will make them much cleaner than today’s combustion engine driven cars.
• Connectivity: More and more customers expect to be fully connected in their vehicles, just like they are today in the office and most homes. In addition, cars will communicate with other vehicles on the road, “see and avoid” pedestrians, communicate with a cities’ infrastructures – to avoid traffic jams and find parking, of course park themselves and offer you valet service.

As an example for driver-less car capabilities in future, Owens talked about the Audi Q5 SUV that drove coast to coast, 3400 miles across 15 states in 9 days, and managed 99% of this distance fully automatically.

As Gary Smith said on Sunday evening, EDA has lots of growth opportunities. Hardware and software for the automotive market will be a major one. ~ Herb

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Indium Corporation’s wafer bumping flux WS-3543 is a low-viscosity semiconductor-grade flux, specifically optimized for uniform solder bump formation across wafers up to 300mm (12 inches) in diameter. WS-3543 washes off completely, even after repeated application, reflow, and cleaning cycles, as may be seen in bump rework and after probe testing.

Testimonial
Indium Corporation’s wafer bumping flux WS-3543 has been used for several years to produce consistent, high-reliability joints in stacked die for 3D memory applications. The viscosity is high enough to form a film over TSV copper-pillar microbumps, yet low enough to be spun onto the wafer with a consistent thickness. As a result, uniform, oxide-free solder bumps are formed across wafers up to 300mm (12 inches) in diameter. In addition, this semiconductor-grade, water-soluble product leaves no residue after DI-water-only cleaning. This eliminates the dangers of delamination, electrical reliability concerns and underfill voiding.

Indium Corporation Website
Date this product was introduced to the market: 2011
Category Product is being nominated for: Materials
Technical Documentation for: Wafer Flux WS-3543

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In the past year, I have written short pieces explaining how Path Finding methodology can proactively help identify viable solutions or reactively identify solutions if something changes during manufacturing. The next few blogs will look at specific examples using a PF tool to help separate the ‘wheat from the chaff’.

Signal Assignments
When I was designing ASICs/SOCs at VLSI Technology, we normally used SSO ‘rules’ to help assign signals, power, and ground to die and package pin outs. In older technologies, this normally produced working solutions; but on designs where the ‘rules’ could not be followed, we manually created SPICE netlists to simulate and validate. Given today’s geometries and various implementation choices (silicon versus glass interposers, metal topologies, via array topologies, etc), using Path Finding tools are preferred.

Path Finding helps optimize cost, power, and area during architectural tradeoffs where 100+% improvements can be realized. From my VLSI Tech days, once architectural choices are made, only 10-20% improvements can be realized during implementation.

Let’s look at a specific example using a software (SW) tool created for accurate and fast Path Finding. For this package test case, a 10×10 via/ball matrix is chosen (top and side profile views) (Figure 1).¹ No silicon die is included for this experiment.

Do signal assignments affect performance and if so, by how much?
To show the impact, I will perform analysis on two different pin assignments that use the same physical structure. Many versions could have been implemented, but this will demonstrate that assignment does matter and should be analyzed before implementation is started. One version will be the classical ‘checkerboard’ where every other via/ball combination is a signal that is separated by a defined return path. Another version will isolate one via/ball in the center surrounded by return paths, forcing all other signals to be on the periphery. This is shown in Figure 2 where the red triangle denotes a port on the top of a via and the purple triangle represents the port on the bottom of a ball. The ‘bow ties’ represent common references placed on the top of a via and the bottom of a ball. Fifty via/ball are used for signals while the other fifty via/ball are denoted for return paths resulting in a Touchstone (s100p) file. Simulation was run from 100MHz up to 20GHz.²

What do the simulation results show?
We will look at both the Insertion Loss (IL) and the Near End XTalk (NEXT) for both pin assignment options. Each company will set the targeted IL and NEXT that their products must meet to correctly operate in the expected environments. As an example: a cell phone will have different criteria than a medical instrument.

Insertion loss measures between two points how much signal degradation occurs.⁴ Whether a signal is transmitted over a cable or on a PCB traces, or through a metal trace on a piece of glass or silicon, IL is a key metric to ensure a working system. All signals will have some degradation due to physical implementation and material properties. Normally with IL, this is analyzed over a frequency range that includes the intended operating frequency range. As the IL increases, the signal received at the far end worsens. The table shows IL for various combinations of Vout/Vin.

Physical Layer (PHY) blocks used for various interconnect standards (USB, SATA, PCI Ex, ZAUI, etc) are perfect examples. Each interconnect standard has various specifications that must be met to support the standard. Some criteria are: voltage levels, operating frequency range, length of cable, how much signal degradation is acceptable, data throughput, etc. The PHY transmits and receives signals. When receiving, it converts signals into binary 0s and 1s that can be recognized. If a signal degrades outside the criteria and cannot be recognized, data such as movies, songs, emails, etc cannot be sent or received.

Below is the IL for both assignments and you can see that the symmetrical checkerboard improves IL by 0.10dB from best to worst IL at 20GHz. But we need to review NEXT. For the isolation signal (ports 57 & 58), we would expect the Non Checkerboard to provide better noise isolation since it is surrounded by return paths.

Near End Cross Talk (NEXT) measures the amount of noise between signals.⁵ As with IL, this is normally analyzed over a frequency range to ensure functionality. Designers should choose signals that are critical to their design (clock signals, wide busses, etc) and place ports on the signal lines that are next to each other. Due to near field electric and magnetic coupling, signal lines can lose energy to each other. This can cause the false switching of quiet lines and a reduction in the insertion loss of the driven line. A NEXT between 0 and -20dB can be too noisy while -25dB is approximately 5% coupling between 2 signals.

For the Checkerboard assignment, the NEXT is consistent between S(13,x), S(71,x) and S(91,x). All show a worst-case NEXT approximately -30dB at 20GHz. But if we look at the Non Checkerboard pattern and review the NEXT for the isolated signal with ports 57 and 58, we should expect and do see a dramatic improvement of 22dB better noise immunity (NEXT = -52dB at 20GHz). But how has this assignment altered the NEXT on other signals? Examining Port 9’s NEXT, we determine that the worst NEXT is now -18dB at 20GHz, 12dB; poorer than the ‘uniform’ NEXT achieved with the Checkerboard pin assignment. Although the Non Checkerboard signal assignment has helped with one signal, other signals have been significantly degraded.

What is learned?

As mentioned earlier, each design and its intended environment will influence what IL and NEXT levels are acceptable. If criteria are not met, physical implementation and/or material changes will be required. Some examples:

• Pin assignment does impact performance, and performance can be enhanced by using isolation (keep out zones) to minimize noise.
• If a specific pair of via/ball responses were examined, increasing pitch can improve both IL and NEXT, but at the cost of growing the area and cost.
• Additional experiments could have also been performed on via/ball pitches to optimize overall IL and NEXT responses.

In addition, vias’ lengths/diameters along with balls’ diameters and whether underfill is used could be additional Path Finding experiments to help optimize design tradeoffs; all performed before costly implementation is performed. Before costly choices are made and implemented, it would be wise spending time performing Path Finding.

In future Path Finding, we will look at wire bonds, PDN, RDL topologies, and complex multi tiered structures (package-on-package). ~ B. Martin

Notes:
1. Creating the basic design required less than 5 minutes to define via and ball profiles, create the array, create a metal layer (pads) between interposer/ball and apply balls.
2. Upper limit on Sphinx 3DPF simulation engine is 100GHz. These simulations were performed on an Intel i7 CPU 870 @ 2.93GHz with 32G of memory. Four (4) CPUs were used and simulated in several hours. Simulation time can be improved by using more CPUs, larger RAM as well as Solid State Drives (SSDs). More info at: http://www.e-systemdesign.com/sphinx3DPF.html
3,4. Professors Swaminathan and Han. Design and Modeling for 3D ICs and Interposers. World Scientific, 2014.

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CIRCL-AP™ is a cluster tool with multiple modules, covering all-surface inspection, metrology and review at high throughput for efficient advanced wafer level packaging (AWLP) process control. The CIRCL-AP provides production-proven, high sensitivity monitoring capability for multiple AWLP applications including 2.5D/3D integration, wafer-level chip scale packaging and fan-out wafer-level packaging.

Testimonial
CIRCL-AP provides differentiated process control to the expanding field of 2.5D/3D manufacturing, helping optimize packaging processes for development of  Cu-pillars, bumps, TSVs and redistribution layers (RDL). CIRCL-AP is currently being used for the ramp of 3D memory stacking for high performance applications, while ongoing collaboration with OSATs is driving improved yield for next-generation WLCSP and fan-out process flows. With a modular configuration, the CIRCL-AP has been adapted to support a wide range of AWLP processes. The 8-Series front side defect inspection and metrology module captures critical defects (e.g. TSV cracks, RDL shorts, deformed or missing bumps and Cu pillars) and provides 2D metrology for RDL, bumps and TSVs. The CV350i edge inspection, profile and metrology module has proven critical for successful implementation of temporary bonding processes—enabling detection of edge trim issues, excessive glue squeeze-out, edge voids and other defects. Finally, the Micro300 module provides X, Y and height metrology for monitoring multiple AWLP applications, including TSV reveal process, RDL line space, micro-bumps and Cu pillars.

KLA-Tencor Website
Date this Product was Introduced to the market: April 2015
Category Product is Being Nominated for: Inspection/Metrology Tools
Technical Documentation for the Circl-AP™

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SOLDERON™ BP TS 6000 Tin-Silver is a lead-free chemistry for solder bump applications. From a single formulation, it is capable of plating speeds of 2-9+ µm/min, tunable composition and the industry’s most robust process window. This flexibility makes it ideal for applications from C4 bumping to micro-Cu pillar capping.

Testimonial
In the latest 2.5D and 3D packaging schemes utilizing copper µpillars, SnAg caps with diameters down to ~10µm are electroplated on top of the µpillars. SOLDERON BP TS 6000 Tin-Silver is capable of WID and WIW of <5%, which represents best-in-class solder chemistry performance. A critical characteristic of solder bumping is bump morphology and composition control, which is relatively easy to manage in larger traditional C4 bump applications. However, as the bump shrinks, the morphology tends to become rough and silver compositions become higher and non-uniform. SOLDERON BP TS 6000 Tin-Silver overcomes this challenge because its additive system was specifically developed to address this issue such that tight distribution of silver compositions and smooth morphology are maintained down to fine feature SnAg plating. As a result, the chemistry helps improve assembly yield and long-term reliability of 2.5D and 3D IC devices.

Dow Electronic Materials Website
Date this Product was Introduced to the market: October 2013
Category Product is Being Nominated for: Materials
Technical Documentation for Solderon BP TS 6000 Tin-Silver Chemistry

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Industry’s first 2.5D/3D security IP from BroadPak provides trusted security and resilience needed for critical 2.5D/3D system integration and prevents hijacking of critical data. This new technology is shifting the paradigm in semiconductor industry and enables chip makers and system companies to develop new generations of secure products. This breakthrough technology prevents reverse engineering of the 2.5D/3D packages and blocks unauthorized access to confidential data.

Testimonial
There is no doubt that 2.5D/3D integration is the future of semiconductor industry, however, 2.5D/3D integration is increasingly vulnerable to security breaches due to globalization of die design, manufacturing and assembly processes and is emerging as catalysis for intruders. Given the breath and magnitude of the threat facing the 2.5D/3D industry, BroadPak security IP was introduced to address the threat at its root. The IP helps proliferate the adoption of 2.5D/3D integration for mission critical applications as well as consumer industry.

Broadpak Website
Date this Product was Introduced to the market: July-9-2014
Category Product is Being Nominated for: Devices (including interposer, 3D IC, 3D Memory, Heterogeneous Integration)
Technical Documentation for 2.5D/3D Package Security IP

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SPTS’s Sigma® fxP, is a well established PVD system used in advanced packaging applications such as UBM and RDL. It utilizes batch degas technology that can improve Rc whilst maintaining high throughputs, despite the outgassing challenges posed from the increasing use of organics, such as mold in Fan-Out WLP.

Testimonial
Fan-Out Wafer Level Packaging (FOWLP) technology is an increasingly popular solution for obtaining a high level of device integration, with a greater number of I/O contacts, at a lower cost. Epoxy mold compound (EMC) is a cost-effective material for accommodating the die/contacts, but readily absorbs atmospheric moisture. This must be degassed prior to RDL metallization processes, otherwise it has a detrimental effect on electrical resistance of the package (Rc). With a low thermal budget (<150°C), an effective degas requires low temperature and long process time – significantly reducing system throughput.

SPTS have implemented a Multi-Wafer Degas solution to eliminate this “degas bottleneck”, which enables a large number wafers to be degassed simultaneously and individually transferred to single-wafer process modules without breaking vacuum. This enhancement for SPTS’s Sigma® fxP ensures low Rc and typically doubles the throughput compared to competing PVD systems, and is being used in full scale 300mm production.

SPTS Website
Date this Product was Introduced to the market: 2010
Category this product is being nominated for:  Manufacturing Equipment (includes handling equipment)
Technical Documentation for Sigma fxP PVD wth Multi-Wafer Degas

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TC-3040 is designed for advanced flip chip devices requiring improved heat dissipation.  The material features a combination of low modulus and high elongation – enabling it to accommodate warpage-induced stresses.  Key to the improved thermal performance : low contact resistance that silicones are known for, along with proprietary filler technology.

Testimonial
While advanced 2.5D or 3D IC are packed with more transistors into confined device space, the device temperature is raised while in operation and the leakage problems worsen. This phenomenon causes a serious challenge to bring 3D IC into high volume production reality. Tested and validated in the IBM Ecosystem, Dow Corning TC-3040 thermally conductive TIM1 gel helps manufacturers keep their device cool. The successful efforts of IBM and Dow Corning scientists have raised the bar for TIM1 performance. This TIM1 gel delivers nearly two times the thermal performance of other industry standard TIMs. It enables the thermal management solution with higher thermal conductivity at 4W/mK, lower thermal resistance performance and excellent under-die coverage, which helps regulate the ever-increasing high-temperature, stressful environments in advanced flip-chip semiconductor packages. As a result, it offers chip-makers broader design options for high-performing yet more reliable 3DIC packages with improved thermal management capability.

Dow Corning Web Site
Date this Product was Introduced to the market: May 2015
Category Product is Being Nominated for: Materials
Technical Documentation for TC-3040

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I recently started watching the HBO sitcom, Silicon Valley. If you haven’t seen it, it’s a great parody of what life in the Valley taken over by socially awkward technology geniuses looks like. It’s pretty funny, and a little bit scary. In one episode, the Pied Piper team is presenting their file compression app demo at TechCrunch’s Disrupt Event. Every presenter claims his or her invention can “make the world a better place.” One of the inventions is a personalized heating system based on microwave technology. One of the judges says, “Is that even safe? I’m pretty sure that’s not safe.” The technologist insists its not harmful, and the benefits to lowering fuel bills will over shadow any negative effects it might have. This may be a scene from a sitcom, but the scary part is, there are influential people in high tech who actually DO think this will make the world a better place. 

While I believe that the Internet of Everything (IoE) is inspired by those who wish to do good, I’m concerned that we could be headed for too much of a good thing. I’m not talking about the security issues and hacking concerns that we’ve all heard about and the industry is working to solve, I’m talking about what living in a world that relies so much on technology will do to our basic humanity. Will we lose our ability to interact and communicate on a human and face-to-face level? Will we lose our perspective of quality of life, as medical innovation allows us to replace parts and extend life in perpetuity – and what effect will that have on society as a whole?

Don’t get me wrong, Amkor, I love you guys, but Chad Jones, the keynote speaker intended to inspire attendees at this year’s Amkor Customer Symposium scared the #$&%* out of me. Truth be told, this keynote made me want to quit my job, throw away my computer and all my handheld devices, and start a food truck business.

Jones, CTO for Deep Information Systems, is known throughout the high tech industry as an entrepreneur, thought leader, and venture capitalist. His talk focused on his observations for the Internet of Things, and he offered a seven-step approach to building complete IoE solutions: identify a business case; create a connected object; build the infrastructure; create applications; create business system integration; analytics and automation; and service and support. The goal, he says, is to “elevate human beings out of doing things that are mundane and tedious.”

“Technology implemented for technology sake is doomed to failure. It must serve a higher purpose,” he said. “Turning something on and off is boring. Connecting a fan with the window blinds to control room climate and lower bills, now that is interesting.” Jones offered a number of real world examples that have followed the steps and have been successful, such as the NEST Thermostat, which provides a gateway to your home via motion sensors that are gesture based, can tell how many people walk by, and controls the temperature based on how many people are in the home. It learns your patterns of behavior, which is a bit too invasive for me. He also talked about the evolution of wearable devices to implantable ones, and that we will soon see such things as implantable smartphones and cyber pills.

In his keynote, Jones talked about Ray Kurzweil, a director of engineering at Google. He is also an advocate for futurist and trans-humanist movements. Jones noted how on the mark some of Ray Kurzweil’s predictions have been so far: back in the 80’s predicting the demise of the Soviet Union thanks to technologies like cell phones and fax machines, that computers would beat the human brain by the year 2000, the explosive growth of the Internet, and the preferred mode of accessing it by wireless systems.

Will Kurzweil’s predictions continue to be similarly accurate? In the 2020’s, he predicts that most diseases will go way as nanobots become smarter than current technologies. Normal human eating can be replaced by nanosystems. The Turing test becomes passable. Self-driving cars begin taking over the roads, and people won’t be allowed to drive manually.

In the 2030s and 2040s, Kurzweil predicts that virtual reality will begin feel 100% real. We will be able to upload our mind/consciousness by the end of the decade. Non-biological intelligence will be a billion times more capable than biological intelligence. Nanotechnology “Foglets” will be able to make food out of thin air and create any object in the physical world.

Are there unintended consequences to what is technically feasible? This is something we need to seriously consider.

How will those of us who grew up in relative anonymity adapt to this connected future, even now, where our every search and purchase is tracked online, where our thermostats know our movements, where we can’t drive our own cars because it will be OUTLAWED, where we communicate soullessly through texts and chats, and real life experiences will be replaced by virtual ones? Where we don’t get to enjoy a dining experience because our nutritional needs will be met by “Foglets” (yuck!). Moreover, how can we ensure that the generations born into this world and don’t know life without the Internet will understand the importance of human connection? Will they accept as standard that their personal information is anything but? That every time they accept “terms and conditions” on a social media website, or take one of those “what Disney character are you” quizzes, they are providing data that can be used to manipulate their decisions? Will they come to rely so much on virtual intelligence that they won’t ever get to develop their critical thinking skills? 

Is this artificially intelligent world we are creating really going to be a better place? Not if we let it take over our lives. We should not be serving our machines, they should serve us. Heck, I don’t even like artificial sweetener, never mind artificial intelligence. My food truck will serve REAL food, not nanosystems. And you are all invited to visit it in person. And the world will be a better place. ~ F.v.T.

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Xpedition® Package Integrator provides a holistic co-design methodology that automates planning and optimization of connectivity from a chip through multiple packaging variables, while targeting multiple PCB platforms. Engineers can quickly and easily assemble complete cross-domain systems (IC, package & board) and drive ball map plans and pin optimization through a rule-based methodology.

Testimonial:
Today’s leading edge IC packaging technologies require a co-design methodology that streamlines the planning, assembly, and optimization of the IC die, package substrate, and PCB while assimilating the physical and logical interactions between each design domain.  Package pin-outs and other packaging interconnect structures, such as bridges and interposers, must not only be optimized based on die level constraints, but also on the constraints, escape routing, and pin-outs of critical interfaces on the PCB. In short, the concept of throwing your design over the wall and letting the next guy deal with it, no longer works.

Implementing a holistic co-design methodology with Xpedition Package Integrator can lead to drastic reductions in the cost of the package (and the board) by highlighting the interactions that impact layer count and size.  The co-design process facilitates communication and improves understanding among the IC die, package substrate and PCB design teams by enabling each team to visualize how the physical and logical connectivity to their design integrates within the full system.

Mentor Graphics Website
Date this Product was Introduced to the market: March 23, 2015
Category Product is Being Nominated for: Design Tools
Technical Documentation for Xpedition Package Integrator

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Nordson ASYMTEK’s programmable Tilt + Rotate 5-Axis Fluid Dispenser dispenses using 5 axes instead of 3. The X and Y tilt enables dispensing from a vertical position, varying tilt angles to all sides of a component and up to the top of a 3D stacked die with high precision and positional accuracy.

Testimonial
Jet dispensing of capillary underfill fluid is a standard process for producing semiconductor packages for its speed, accuracy, and dispense weight process control. Ensuring adequate underfill at the top layer of a 3D die stack is critical to the long-term reliability of the package. Tilt jetting along the vertical surface delivers underfill fluid precisely to this top layer and reduces wet-out distance from the die edge. The Tilt + Rotate feature on Nordson ASYMTEK’s Spectrum® II dispensing platform is an enabling factor for mass production of latest generation 3D stacked-die devices with precise weight control, accurate fluid placement, and high throughput. Integrated software controls on the Spectrum II automatically actuate the valve position during production for operator-independent jetting along the vertical surface to all four sides of a 3D die stack. Tilt jetting on the Spectrum II enables fluid placement right where it’s needed and avoids places where it’s not.

Nordson ASYMTEK Website
Date this Product was Introduced to the market: March 2015
Category Product is Being Nominated for: Manufacturing Equipment (includes handling equipment)
Technical Documentation For Programmable Tilt + Rotate 5-Axis Fluid Dispenser

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SABRE® 3D is a next-generation electroplating product designed to meet leading-edge production requirements for advanced packaging applications.  This product leverages proprietary front-end manufacturing technology and offers market-specific solutions for copper pillar and through-silicon via (TSV) fabrication.  SABRE 3D offers industry-leading throughput along with reduced cost of consumables to enable high economic value for customers.

Testimonial
Electroplating is one of the most challenging process steps for TSV fabrication.  Lam’s SABRE 3D enables the fastest and most consistent TSV fill rate on a production-proven hardware platform to ensure void-free fill at lowest cost of ownership.  Specific innovations to reduce cost of TSV manufacturing are listed below:

• Fast fill rate (25% higher) and wide process window for various features and geometries
• Proprietary advanced pretreatment technology enables uniform wetting to ensure high yield
• Superior fill quality with void-free fill across range of different aspect ratios
• Excellent process stability with advanced hardware and plating bath control, including an advanced dosing algorithm that ensures a stable process over extended wafer runs
• Modular design along with stacked architecture enables maximum footprint efficiency in the wafer fab
• Industry-leading productivity with up to 50% lower cost of ownership compared with competitive offerings.

Lam Research Website
Date this Product was Introduced to the market: July 2011
Category Product is Being Nominated for: Manufacturing Equipment
Technical Documentation for Sabre 3D

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2015 will go down in history as the year 3D finally got real. It’s not an emerging technology anymore, and as such isn’t a main feature at the 2015 SEMICON West, which gets underway next week, July 13-16, 2015 at the Moscone Center in San Francisco. Rather, this year 3D topics are integrated throughout the program. With a little digging, I pulled together this year’s guide. Here’s where you’ll find me spending my time in between briefings:

Monday July 13, 2015 – imec ITF USA, Noon-6pm
This year, imec’s ITF theme is For the Builders of Tomorrow: Materials and Device Innovation for Smarter Livings. Topics span the spectrum from the Internet of Things (IoT), Silicon Photonics, to disruptive materials and lithography. Presenting imec’s update on 3D integration will be Eric Beyne, who will present 3D Technology Driven by 3D Application Requirements: a 3D Landscape. Beyne will discuss the relationship between 3D technologies and the system-level interconnect hierarchy.

Tuesday, July 14, 2015
On Tuesday morning, after the SEMI Press Conference, I plan to hit the Semiconductor Technology Symposium (STS) session (10:00-12:30), Packaging, the Very Big Picture, to hear Bill Bottoms update us on the ITRS 2.0. I’m also looking forward to the latest from AMD’s Bryan Black on the company’s recently launched Fiji XT, the GPU with High Bandwidth Memory (HBM) stacks. The panel session, Value vs. Cost, moderated by Sesh Ramaswami, Applied Materials, and featuring panelists from AMD, 3MTS, Comcast, and Oracle also promises to be thought provoking from a 3D perspective.

Tuesday afternoon, somebody save me a seat at the TechXpot North session (1:30pm – 3:40pm), Emerging Generation Memory Technology: Update on 3DNAND, MRAM and RRAM, featuring speakers from Micron, Tezzaron, Crossbar and Everspin, as well as Analyst Jim Handy, who will discuss the cost aspect of tomorrow’s memories.

If you are unable to attend LetiDay, Going Vertical, from 5-8pm, (which is the most 3D you’ll get in three hours) because it’s invitation only, I will be briefing some of the key speakers and will cover the key takeaways in a post-SEMICON West blog post.

Wednesday, July 15, 2015
My Wednesday will start with the Keynote by Doug Davis, Intel, who will talk about the IoT and the next 50 years of Moore’s law, and the rest of the day I will be in briefings.

Thursday, July 16, 2015
I hope many of you will join us at the 3rd Annual 3D InCites Awards Breakfast, from 8-10am, to participate in the presentation of this year’s awards, as well as the first ever 3D InCites Individual Achievement Award. The recipient of this award was nominated and selected by our 3D InCites Award judges, to be recognized as an individual who has been instrumental in the commercialization of 3D integration technologies. The guest speaker of this year’s breakfast is Scott Jones, Alix Partners, who will talk about how 2.5/3D Technologies Will Shake Up the Semiconductor Supply Chain and Cost Structure. Space is limited, so please book your spot today.

Lastly, I plan to catch GlobalFoundries’ Ramakanth Alapati, who will be presenting, 3D IC Technology Past, Present an Future, on Thursday morning from 11:30-11:55, as part of STS, Path to Future Interconnects session. This talk examines 3D IC technology of the past, present and future using cost/performance as a metric.

I’m pretty sure this line-up  will give me plenty to write about in the weeks after SEMICON West. See you at the show! ~ F.v.T.

The post The 2015 3D InCites Guide to 3D at SEMICON West appeared first on 3D InCites.

One of the ways to build more complex, powerful, and cost-effective electronic systems is stacking chips on top of each other. Imec recently compared the two main options for going 3D: interposer-based stacking and 3D stacking. The goal of the exercise was to detect whether the stacking and packaging processes for the two options result in a different yield, and where in the processes those differences originate.

Chip stacking yield is a major cost indicator, so any improvement will directly relate to the stack’s profitability. The results revealed two instances of yield loss. During 3D stacking, there is a loss when the two chips are bonded with thermo-compression. This is due to the particular distribution of forces during the compression. And the interposer-based stacks show a known yield loss for the second chip, which is bonded later than the first. This can be prevented by adding a NiB (nickel-boron) capping layer to the interposer’s microbumps.

Building the test chips
The advantage of having both research, design, and processing in-house is that we can test all options by designing dedicated test chips, fabricated in-house. For this experiment, we built our 3D stacks starting from a 65nm CMOS test chip, which we call Package Test Chip version Q (PTCQ) (Figure 1).

Figure 1 – Build-up of 3D stacked IC and 3D interposer-based IC with 65nm CMOS test dies

The particular design of this chip allows us, among other things, to investigate the yield of the chip’s connections in the stack. Foremost, these are the microbump connections between two chips layers. But we also look at the package bumps: the connections of the 3D stack with the package and the outside world. In addition, the chip also contains heaters to investigate the thermo-mechanical behavior of stacks.

Testing the connection between stack layers is done through loop back structures. These are two points of contact that are interconnected on the chip. With 832 loopback structures covering the whole connected surface of the chip, we can then make a map of functional and blocked loopback structures at each stage in the process.

The two major ways of stacking chips that we tested are 3D stacking and interposer-based stacking (Figure 2). In the former, the dies are added on top of each other, building a tower of chips. In the latter die dies are stacked next to each other on an interposer, a common ground floor.

Figure 2: 3D interposer-based IC and 3D stacked-IC before package molding.

The test chip was made in two versions. One is to serve as top die of the stack, where it will sit face-down with its metal layers connected to the lower chip through microbumps. This PTCQ chip is 200µm  thick and has CuNiSn microbumps with a diameter of 15µm. The second version will serve as bottom chip of the ‘3D stacked IC’ stack. Again, face down, its metal layer is connected to the outside world through Cu pads with 50 micrometer diameter. On its backside however, it is thinned down to 50 micrometer, revealing the through silicon vias (TSVs) that were etched through the chip’s body and that connect with the chip’s circuits. These TSVs are a mere 5µm wide and are crowned with Cu microbumps of 25µm diameter, making them ready to contact the 15µm microbumps of the upper chips.

In the interposer-based stack, this second version of the PTCQ test chip is replaced by the interposer chip. This chip is both larger (it will house several chips next to each other) and simpler (it just makes the TSV connections between the chips; it doesn’t need any transistors).
So in both stacks, the 15µm bumps of the top chip will have to be aligned and bonded to the 25µm bumps of the lower chip, with a 40µm pitch. The actual bonding is done through thermo-compression. The bonding force corresponds to a pressure of around 69MPa applied to the 37,000 microbumps of a test chip. The highest temperature reached is 270℃ 38 degrees above the melting point of Sn.

Comparing the yield
With these test chips ready, the yield exercise was started. The way we did this was to go through the whole process of fabricating 3D chip stacks, focusing on the 3D-enabling technologies: wafer thinning, thin-wafer handling, TSV and microbump processing, and stacking and packaging. At various stages in the processing, we measured the yield: the percentage of 3D chips that functions correctly. Where there were any differences, we tracked the possible causes.

Stacking a first test chip on the interposer resulted in a near 100% yield. But the yield of stacking a test chip on a second, thinned test chip is slightly lower. This was revealed by the test structures, where we did find some open loopback circuits at the corners and edges of the chip-on-chip stack.

There are two differences in the stacking process that can explain this difference. First, the thinned-down test chip is thinner (50µm) than the interposer (100µm). This makes it more flexible under the applied compression. Second, the layout of the copper pads that serve to connect the stacks to the package is different. In the thermo-compression process, these pads are the only contact with the tool. They translate the bonding force to the microbumps on the other side of the chip. But some of the microbumps at the edges and corners of the die fall outside the area where the larger copper pads are. As a result, these receive less force, especially with the thinner, more flexible die. So this leads to a number of microbumps that stay unconnected in the chip-on-chip package.

A second yield-loss effect was known beforehand: Stacking two dies on the interposer is done in two cycles. Without additional measures, the Cu microbumps on the landing site for the second die will oxidize during stacking of the first die. A way to overcome this is by plating NiB on the interposer microbumps before stacking. In our test, we measured the difference in yield between the ‘raw’ process and the one where we microbumps are plated. In the first case, there is a substantial yield loss, which is completely regained with the NiB plating.

Yield as a cost determinant
Yield, and more specifically the compounded yield of all stacking steps, is one of the most important factors determining the cost of 3D stacking. So determining and solving hidden yield problems in either stacking method will have a direct effect on the cost (and profitability). With this experiment we have shown how appropriately designed test chips can help to compare various stacking processes and to uncover sources of yield loss. ~imec

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GRENOBLE, France – July 09, 2015 – IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip, called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).

The 3DNoC chip is based on a 2D die that can be used in a stand-alone applicative mode, and also in a 3D stack with several dice, to multiply the processing performance of the system. The project’s complete demonstration platform shows both the simulated and measured thermal effects in the 3D chip using a new Mentor Graphics® Calibre® thermal-analysis prototype.

“The technology developed for this realization can be easily used and transferred to address mixed-technology applications, such as imagers and RF transceivers, or complex digital processing, such as high-performance computing and programmable devices,” said Severine Cheramy, IRT 3D program director. “In parallel with these results, we are working on developments that address more fine-pitch 3D technology than those used in the 3DNoC demonstrator and solutions for thermal dissipation, temporary bonding and stress issues.”

3D-stacking technology is a promising solution to improve both performance and density integration without requiring transition to the next technology node. It allows the integration of different technologies and simplifies the use of small-sized dice to improve modularity and increase yield. In a complex and traditional 2D SoC, the technology node is defined by the most complex function, and reuse methodology is done at the IP level. A 3D system blends several technologies and reuse methodology can be performed at the elementary die, the “chiplet.”

The 3DNoC chip was defined and designed by Leti, with the direct support of STMicroelectronics, using a specific add-on 3D design kit and a set of 3D sign-off verification tools provided by Mentor Graphics. CMOS technology, 3D technology and packaging were realized by ST and Leti, with a “via-middle option” in 65nm CMOS technology. The test and demonstration platform is a joint development among the three partners.

Proving the viability of 3D stacking
IRT Nanoelec provides a multi-skill environment – including technology development, innovative processing architecture, and specific design tools in a global system- methodology approach – for the development of pioneer 3D demonstrators to prove the viability of 3D stacking in a wide range of applications. Although the 3DNoC chip addresses baseband processing, all technology and design bricks are reusable across a range of other applications.

3DNoC is the first worldwide realization of a 3D-scalable processor chip. It goes beyond prior state-of-the-art as a 3D asynchronous communication network that can exploit the maximum performance of vertical links and offer an aggregate 3D network link bandwidth of 450 MByte/s. The strategy, which is based on increasing the performance of a system by stacking several identical dice in the same footprint, is very similar to HMC or HBM memories. In the case of DRAM, byte capacity is multiplied by the number of elementary dice stacked; the 3DNoC circuit multiplies processing performance.

The Technology
Several identical 65nm CMOS digital dice can be bonded using a face-to-back technology to build a stack of processing elements, using 10µm-diameter through-silicon via (TSV) and 20µm-diameter µpillars and µbumps. In the IRT Nanoelec demonstration, two dice are stacked.

At the elementary die level, provisions were made to allow the stacking of up to four dice: the number of power connections is dimensioned in this way, while the number of signals is constant regardless of the number of stacked dice. Area occupied by the 2,000 TSVs represents about 1 percent of the whole die area (72 mm²) and wafers are thinned to 80µm for TSV revelation at the backside.

3DNoC is mounted in a 581-ball, 0.3mm-pitch BGA package using a stacking-last approach, i.e. the bottom die is bonded on the substrate and after the top one on the bottom.

Targeting digital baseband processing
The digital modules embedded in 3DNoC are computing-intensive IPs, processor cores and programmable DMA engines connected to the NoC routers using a dedicated interface compatible with a packet-switching mechanism.

The global architecture was partitioned in a scalable way to address several modes, depending on the number of antennae used for transmitting-and-receiving levels. The modular elementary die was sized to fit the processing performance required to support the single antenna mode and, by stacking two or four dice, more complex multiple antenna modes are supported. As an example, the 3DNoC chip developed in this project can support up to two antennae for both TX and RX.

Network on Chip (NoC)
For many years, network-on-chip (NoC) has played a key role in 2D complex SoCs, thanks to its ability to efficiently manage data exchanges between many IPs. The fact that packet switching communication is well decoupled to computing IPs makes the extension of the interconnection capabilities to the third dimension easy and natural. The elementary die of the 3DNoC integrates four 3D routers to ensure vertical communication.

Redundancy and fault-tolerance are used in the 3DNoC circuit at both communication and processing levels. Using asynchronous logic for router implementation allows implementing robust 3D communication interfaces without any delay assumption, and makes dynamic voltage and frequency scaling (DVFS) for power optimization easier, relative to processing requirements and thermal constraints. Specific analysis and sizing tools developed by Mentor Graphics for power and thermal aspects were very helpful to architects in the 3D floor plan of the 3DNoC chip. More specifically, the Calibre® 3DSTACK tool has been used for final sign-off verification of the 3D assembly of the two dice.

Several modules have been designed to ensure 3D signal integrity between the different tiers: micro-buffers, ESD protection, 3D link redundancy and data coding. A complete design-for-test methodology has been set up to perform a hierarchical test of each module, tier and stack before and after stacking based on the Mentor Graphics Tessent® test tool suite including test pattern generation.

About IRT Nanoelec
Nanoelec Research Technological Institute (IRT), headed by CEA-Leti, conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics. Working within the framework of programs with investments on future technologies, it leverages Grenoble’s proven innovation ecosystem to create the technologies that will power the nanoelectronics of tomorrow, drive new product development and inspire new applications – like the Internet of Things – for existing technologies. The R&D conducted at IRT Nanoelec provides early insight into how emerging technologies such as 3D integration and silicon photonics will affect integrated circuits.

In addition to its R&D activities, IRT Nanoelec runs a technology-transfer program set up to ensure that the innovations developed directly benefit businesses — especially small and mid-sized businesses — in all industries. IRT Nanoelec also offers educational and training programs to develop the micro- and nanoelectronics competencies businesses will need to remain competitive in tomorrow’s global markets. Visit www.irtnanoelec.fr

IRT Nanoelec Contact Information:
Didier Louis :
didier.louis@cea.fr
+33 6 32 44 64 31

Mentor Graphics, Calibre, and Tessent are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

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What is heterogeneous integration, and is it my friend, or is it my foe?

Why does it seem everywhere one looks, heterointegration is standing up and being counted right now, in mid-2015?

And what kind of doors is heterogeneous integration opening for microelectronic technologies beyond, complementary to, or in competition with Moore’s Law silicon-based semiconductors?

Dr. Peter Ramm, Fraunhofer EMFT, writing in 3D InCites on January 16, 2015, noted that “There are certainly different understandings in the microelectronics community regarding the definition of heterogeneous 3D integration.”

According to Ramm, heterogeneous integration can be defined as the integration of different devices, such as a CMOS processor and a memory; heterointegration can also be defined as the integration of components with significantly different device technologies as e.g. CMOS and MEMS; and, finally, heterointegration can be defined as the integration of different substrate materials, e.g. GaAs / silicon.

From a materials integration perspective at the materials integration level it could also be InGaAs / silicon, or InP / silicon, the motivation say for use in high mobility transistors; or maybe it’s fully-formed III-V photonic components integrated with silicon logic, as IBM recently announced, and as was covered in the EETimes piece “IBM Demos CMOS Silicon Photonics.”

“’We’ve been doing silicon photonics research since 2000 because we understand all the opportunities they have for processing data. We believe our efforts will result in the first marketable chip to put CMOS and silicon photonics on the same chip,’ Supratik Guha, director of Physical Sciences, IBM Research told EE Times.”  “’The lasers are brought in from off-chip in order to be modulated, but eventually we hope to incorporate III-V lasers right on the chip,’ Will Green, manager of the Silicon Photonics Group at IBM Research … .”

Why the visible new posture for heterogeneous integration?  That’s possibly the result of the work being promoted by the ITRS Heterogeneous Integration Focus Team, as part of an ITRS 2.0 refresh.

Writing in Solid State Technology, the team says its mission is to “ … provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the requirements for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.”

About those difficult challenges, the ITRS heterointegration focus team thinks “The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS.”

Visibility for heterogeneous integration? When the ITRS talks people listen.

And when DARPA talks people listen too.

DARPA, which has possibly influenced the course of semiconductor technology more than any other single organization, is working again on the bleeding edge of technology (and raising heterointegration’s visibility) with its latest Heterogeneous Integration of III-Vs and Silicon project(s), aka Diverse Accessible Heterogeneous Integration, DAHI.

In a presentation made to CS International in March 2015, Dr. Daniel Green, program manager, Microsystems Technology Office, DARPA, related how DAHI is seeking to heterogeneously integrate InP HBTs, GaN HEMTs, and RF MEMS with sub-micron silicon CMOS to reach “unprecedented levels of performance (e.g. bandwidth, dynamic range, power consumption).”

In Dr. Green’s example, the heterointegration of III-V components with 130nm CMOS (trailing edge CMOS these days, and cheap) is expected to achieve the same kind of functional performance as a silicon device five process nodes further down the line (28nm; not so cheap).

That’s the kind of result that deserves to stand up and be counted, and is very much along the lines of what others are proposing – to repurpose trailing edge CMOS running on 200mm wafers in order to add new value.  (For more on this please see the piece “IoT Requires the Evolution of the “New” 200mm Fab.)”

Or is heterointegration’s new visibility the result of a current commercial success, success always being a convincing trophy to bring to any table?

Consider the Apple iPhone 6 and 6 Plus.  You may have received one for the holidays, or maybe someone you know did.

Apple shipped approximately 75M units of those phones in the fourth quarter of 2014; each phone has two camera modules, one front, one rear, and each of those camera modules contains a heterogeneously integrated CMOS Image Sensor.

“The Sony ISX014 8MP sensor features 1.12um pixels and integrated high speed ISP. The pixel layer and logic layer part are manufactured as separate chips and stacked by using TSVs. Previously the pixel and logic circuit of Sony’s back side illuminated (BSI) CMOS image sensor were formed during the same fabrication process.” (Dr. Phil Garrou, Solid State Technology.)

That’s 150M units of a 3D heterogeneously integrated component shipped into the consumer electronics market by one smartphone supplier in just one quarter.

Stand up and be counted.

Whether the camels’ nose has entered the tent, or whether there’s now a foot in the door, or whether we are now seeing the thin end of the wedge, Moore’s Law silicon semiconductor technology, with its increasing limitations (cost; benefits), will soon, if it has not already, find itself in a competition, or a coopetition, with heterogeneous integration.

According to the ITRS 2.0 team, “Overcoming these [Moore’s Law] limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.”

Heterointegration’s impact will be in mobile products, in big data systems and in the cloud; and in biomedical products, green technology, and in the Internet of Things.

That’s called the future, and it’s heterointegration, friend or foe, opening the door.

From Pittsburgh, PA, thanks for reading.  ~PFW

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